Parallel decoding algorithms are used to reach high throughput in a receiver. In parallel decoding, a plurality of processors are employed to commonly decode received coded data stored in one or more memories. In coding schemes involving an interleaver operation, two or more processors may require access to the same memory on a given clock cycle, resulting in a memory contention. Memory contention reduces the throughput of the decoder.
As a remedy, so-called contention-free interleavers may be used. However, the use of such interleavers must be part of the standard and can not be introduced belatedly. Another way to address the problem of memory contention is to enhance the number of memories, thus reducing the probability of memory access collisions. However, this increases hardware complexity.
For these and other reasons there is a need for improved receivers that reduce or eliminate memory contention.